FIG. 1 shows a typical flash memory device 100 including blocks of flash memory cells. The elements of one example block 102 include an array of flash memory cells 103. An array of eight by eight flash memory cells is illustrated in the example block 102 for simplicity of illustration and description. However, a typical block would have more numerous flash memory cells.
Each flash memory cell 103 has a control gate, a drain, and a source. The control gates of all flash memory cells in one row are coupled to a same word-line. The drains of all flash memory cells in one column are coupled to a same bit-line. Thus, the example block 102 has the eight word lines WL0, WL1, . . . , and WL7 for the eight rows of flash memory cells. In addition, the example block 102 has eight bit lines coupled to eight select MOSFETs (metal oxide semiconductor field effect transistors) 104.
Furthermore, the example block 102 has a local X-decoder 106 for activating one of the word lines WL0, WL1, . . . , and WL7. For accessing one of the flash memory cells in the block 102, a selected one of the word lines WL0, WL1, . . . , and WL7 is activated when a boost voltage VBST is applied thereon by the local X-decoder. Additionally for accessing that flash memory cell, one of the select MOSFETs 104 coupled to the drain of that flash memory cell is turned on for applying a boost voltage YBST thereon. The sources of the flash memory cells are coupled to a low supply voltage VSS.
Further referring to FIG. 1, the local X-decoder 106 applies the boost voltage VBST on the selected one of the word lines WL0, WL1, . . . , and WL7 using the controls signals PGW and NGW from a global X-decoder 108, WLG from a vertical block decoder 110, and eight word-line voltages AVW0, AVW1, . . . , and AVW7 from a vertical word line decoder 112. The PGW signal indicates whether a flash memory cell within the block 102 is to be accessed for an operation such programming, and NGW is the reverse logical state of PGW. The global X-decoder decodes block row address bits from an address sequencer (not shown) for generating PGW and NGW that are applied across a row of blocks such as 102 and 114 in FIG. 1.
The WLG indicates whether a column of blocks such as blocks 102 and 116 are being accessed. The vertical block decoder 110 decodes vertical block address bits from the address sequencer (not shown) for generating WLG applied across the column of blocks 102 and 116 in FIG. 1.
The vertical word line decoder 112 decodes vertical word line address bits from the address sequencer (not shown) for generating eight word-line voltages AVW0, AVW1, . . . , and AVW7 applied across the column of blocks 102 and 116. In addition, the drain bit line boost voltage YBST is applied on the selected drain bit line across the column of blocks 102 and 116. FIG. 1 shows an array of two by two blocks for the flash memory device 100, but typical flash memory devices typically include more numerous blocks.
FIG. 2 shows an example implementation 106A of the local X-decoder 106 as disclosed in U.S. Pat. No. 6,646,950. The local X-decoder 106A inputs the control signals PGW, NGW, WLG, AVW0, AVW1, . . . , and AVW7 from the decoders 108, 110, and 112. The local X-decoder 106A then applies a boost voltage VBST on one of the word lines WL0, WL1, . . . , and WL7 when the PGW is a logical high state.
Referring to FIG. 2, the local X-decoder 106A includes a respective driver for each of the word lines WL0, WL1, . . . , and WL7. Thus, a first driver 120 is for the first word line WL0, a second driver 121 is for the second word line WL1, . . . , and so on until an eighth driver 127 is for the eighth word line WL7.
Each driver, such as the first driver 120, includes a driving MOSFET (metal oxide semiconductor field effect transistor) 132 and a pull-down MOSFET 134 coupled in series. The driving MOSFET 132 has a drain coupled to a corresponding line voltage AVW0 from the vertical word line decoder 112. Thus, the driving MOSFET within the second driver 121 is coupled to the corresponding line voltage AVW1, and so on until the driving MOSFET within the eighth driver 127 is coupled to the corresponding line voltage AVW7.
Further in the example driver 120, the source of the driving MOSFET 132 is coupled to a drain of the pull-down MOSFET 134. The source of the pull-down MOSFET 134 is coupled to a low voltage VSS. The control signal NGW from the global X-decoder 108 is coupled to the gate of the pull-down MOSFET 134. The example driver 120 also includes a control MOSFET 136 having a source coupled to the gate of the driving MOSFET 132 at a control node 138.
Further referring to FIG. 2, each of the drivers 120, 121, . . . , and 127 are each implemented similarly with a respective control MOSFET, a respective driving MOSFET, and a respective pull-down MOSFET. The PGW control signal from the global X-decoder 108 is applied on the drains of the control MOSFETs in all of the drivers 120, 121, . . . , and 127. The WLG control signal from the vertical block decoder 110 is applied on the gates of the control MOSFETs in all of the drivers 120, 121, . . . , and 127.
For driving one of the word lines WL0, WL1, . . . , and WL7 to a boost voltage VBST, the controls signals PGW and WLG are set at the boost voltage VBST. Assume that the first word line WL0 is to be activated to the boost voltage VBST. In that case, initially, the AVW0 is set to the low voltage VSS while the control signals PGW and WLG are set to the original boost voltage VBST. With such voltages, an initial boost voltage (VBST−Vth) is generated at the control node 138, with Vth being the threshold voltage of the control MOSFET 136.
Thereafter, with the control signals PGW and WLG still set to the original boost voltage VBST, the AVW0 is set to the original boost voltage VBST such that a final boost voltage (VBST+ΔV) is generated at the control node 138, with ΔV being about the gate to source voltage of the driving MOSFET 132. In this manner, the original boost voltage VBST is generated on the word line WL0 without degradation of the voltage level from the gate to source voltage drop for the driving MOSFET 132 when the AVW0 is set to the original boost voltage. On the other hand, if the AVW0 is the low voltage VSS, then the word line WL0 is discharged to the low voltage VSS.
The respective control MOSFET, the respective driving MOSFET, and the respective pull-down MOSFET within each of the other drivers 121, . . . , and 127 operate similarly. Thus, the corresponding word line WL is activated to the boost voltage VBST if the corresponding line voltage AVW is the boost voltage, or is discharged to the low voltage VSS if the corresponding line voltage AVW is the low voltage VSS, for each of the drivers 120, 121, . . . , and 127.
When the NGW is activated to the boost voltage VBST (with the PGW being deactivated to the low voltage VSS), the driving MOSFETs are turned off, and the pull-down MOSFETs are turned on in all of the drivers 120, 121, . . . , and 127. In that case, each of the word lines WL0, WL1, . . . , and WL7 is discharged to the low voltage VSS.
In the local X-decoder 106A of FIG. 2, each of the drivers 120, 121, . . . , and 127 is implemented with a corresponding control MOSFET 136 for stepping up the control voltage at a respective control node 138 from the initial boost voltage (VBST−Vth) to the final boost voltage (VBST+ΔV) that is higher than the original boost voltage VBST. Thus, eight such control MOSFETs and eight separate such control nodes are used in the eight drivers 120, 121, . . . , and 127 in the prior art of FIG. 2, resulting in increased area and wiring complexity.